Integrated circuits (IC) typically are made of a number of Intellectual Property (IP) blocks (e.g., reusable units of logic that may be used generically in numerous applications) blocks that perform various functions. The IP blocks collectively define the overall functionalities of the IC. IP blocks are tested using a plurality of testing methods. One of the testing methods includes marginal defect testing. Marginal defect testing involves checking for failures on the circuitry that arises from variations in the resistances, capacitances, and other properties. Existing circuits and techniques for marginal defect testing limit our ability to test efficiently and to test IP blocks with different clock polarities. For example, when testing an IC which includes logic circuit that can only be tested using at least three at-speed clock pulses and also having logic circuit that can be tested using only two at-speed clock pulses, existing circuits and techniques require the testing of the both logic circuits to be performed using three at-speed clock pulses, which is inefficient. “At-speed clock pulses” refer to clock pulses that are generated, and applied to circuitry utilizing the clock pulses, at approximately the same frequency (e.g., speed) as the circuitry is designed to operate at. While testing of some logic may be possible using clock pulses at lower than normal operating frequencies, such testing may not detect defects that only appear at normal operating frequencies.
It is within this context that the embodiments described herein arise.